0. both binary and structural compatibility with existing Power4
1. CMP(Chip Multi-Processor), 2 cores
2. SMT(Simultaneous Multi-Threading), 2 threads per core (greater use of chip resources but consumes greater power)
3. Interconnections
Shared L2 cache, with crossbar-like switch between cores and L2(CIU, Core Interface Unit)
Shared Bus Fabric, to maintain coherence between L2, memory and I/O units.
4. 4 intructions issues per clock per core
5. Cache
L1: 64/32KB per core
L2: 1.9MB shared
L3: 36MB (off-chip)
6. 17.2 GB/s Peak memory bandwidth
7. 1.9GHz Clock rate
8. 276M Transistors
9. 389 mm^2
10. 125W Power
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